1. Field of the Invention
The invention relates generally to analog-to-digital converter (ADC) circuits and, more particularly, to calibration of pipelined ADC circuits.
2. Description of the Related Art
Analog-to-digital converters (ADCs) and their counterpart digital-to-analog converters (DACs) are an important class of electrical systems. They are ubiquitous in electrical circuits, having applications ranging from automotive systems to advanced communication systems. Just as the name conveys, ADCs accept a continuous analog signal and convert it to a discrete digital signal. DACs perform the reverse operation. A good ADC recreates an analog signal digitally while maintaining the integrity of the original signal and limiting information loss to an acceptable level.
Several different design approaches have been utilized to realize ADC circuitry, such as flash converters, single- and dual-slope integrating converters, and tracking converters. Each of these designs offers various advantages over the others. Some important characteristics of ADCs include resolution, conversion rate or speed, and step recovery. Resolution is the number of binary bits output by the converter. Speed is a measure of how fast the converter can output a new binary number. In discrete time systems and digital signal processing, bandwidth is associated with the sampling rate, and the term is often used to describe the speed of such a system. Step recovery is a measure of how fast a converter can react in response to a large, sudden jump in the input signal.
One type of ADC, a flash converter, is formed as a series of comparators, each having an associated reference voltage. The input signal is continually compared to the series of increasing reference voltages. For any given input voltage, a corresponding set of comparators will output a signal which is then fed into a priority encoder circuit, producing a binary output. Flash converters usually operate at high speeds (high bandwidth) with good step recovery but have relatively poor resolution.
Single- and dual-slope ADCs use an op-amp circuit configured as an integrator to generate a saw-tooth waveform which serves as the reference signal. The amount of time that it takes the reference signal to exceed the input signal is measured by a precisely clocked digital counter. Integrating converters have good resolution but are generally slower than other designs.
A third type of ADC is the tracking variety. The tracking converter uses a DAC and an up/down counter to generate the digital signal. The counter is continuously clocked and feeds its output into the DAC. The analog output of the DAC is then fed back and compared to the input signal using a comparator. The comparator provides the high/low signal necessary to cause the counter to operate in “count up” or “count down” mode, allowing the counter to track the input signal in discrete steps. Tracking ADCs have acceptable resolution and high bandwidths but suffer from poor step recovery.
Another popular implementation is a multi-tiered architecture called a pipelined ADC. The pipelined ADC uses two or more steps of subconverting. First, a coarse conversion is done yielding the most significant bits (MSBs). Then, a comparison is made between the digital signal and the original analog input. The difference between these two signals, the residue, is then converted at a finer level to get the least significant bits (LSBs). The coarse and fine conversions are then combined using an encoder.
In some ADCs, a dither is used to improve performance. Dither is a relatively small random signal that is added to the input before the conversion is done. Dither is designed to cause the state of the LSB to oscillate between high and low. This allows the system to process lower level signals, rather than simply cutting off the signal at these lower levels. Thus, the range of signals that the ADC can convert is extended at the expense of a small amount of noise. The quantization error resulting from the noise is diffused across many clock cycles, resulting in an accurate representation of the original signal over time.
Several calibration techniques for pipelined ADCs are known in the art. Some of these known techniques correct for errors due to the capacitor mismatch and the operational amplifier finite gain. In some previous techniques, the error was usually dominated by the capacitor mismatch due to relatively low operating speeds. Some of those techniques involved injecting dither in the MDAC that is uncorrelated with the input signal. (See E. J. Siragusa and I. Galton, “Gain error correction technique for pipelined analogue-to-digital converters”, Electronics Letters, 36, pp. 540-544, July 1996; J. Ming and S. H. Lewis, “An 8b 80Msample/s pipelined ADC with background calibration”, IEEE ISSCC, pp. 42-43, 2000). The dither signal sees the same error as the input signal, and because the dither signal is uncorrelated with the input signal, the dither can be separated digitally by correlating it out. This may be done with a digital correlator (see Siragusa et al.) or using an LMS algorithm (see Ming et al.).
One disadvantage of known dither techniques is that the dither signal consumes a portion of the dynamic range of the system subcomponents, namely the digital-to-analog converter (DAC) that is used within the various stages of the pipelined ADC. Typically, the dither signal is about half the size of the correction range, resulting in a power penalty of about 50% for the DAC where the dither is introduced. (See Siragusa et al.; Ming et al.). This makes the dither calibration technique undesirable for nanometer CMOS processes where dynamic range is a premium commodity.